// Copyright (C) Kumo inc. and its affiliates.
// Author: Jeff.li lijippy@163.com
// All rights reserved.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Affero General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU Affero General Public License for more details.
//
// You should have received a copy of the GNU Affero General Public License
// along with this program.  If not, see <https://www.gnu.org/licenses/>.
//

// From Apache Impala (incubating) as of 2016-01-29. Pared down to a minimal
// set of functions needed for Apache Nebula / Apache parquet-cpp

#pragma once

#include <cstdint>
#include <memory>
#include <string>

#include <turbo/base/macros.h>

namespace nebula {
namespace internal {

/// CpuInfo is an interface to query for cpu information at runtime.  The caller can
/// ask for the sizes of the caches and what hardware features are supported.
/// On Linux, this information is pulled from a couple of sys files (/proc/cpuinfo and
/// /sys/devices)
class TURBO_EXPORT CpuInfo {
 public:
  ~CpuInfo();

  /// x86 features
  static constexpr int64_t SSSE3 = (1LL << 0);
  static constexpr int64_t SSE4_1 = (1LL << 1);
  static constexpr int64_t SSE4_2 = (1LL << 2);
  static constexpr int64_t POPCNT = (1LL << 3);
  static constexpr int64_t AVX = (1LL << 4);
  static constexpr int64_t AVX2 = (1LL << 5);
  static constexpr int64_t AVX512F = (1LL << 6);
  static constexpr int64_t AVX512CD = (1LL << 7);
  static constexpr int64_t AVX512VL = (1LL << 8);
  static constexpr int64_t AVX512DQ = (1LL << 9);
  static constexpr int64_t AVX512BW = (1LL << 10);
  static constexpr int64_t AVX512 = AVX512F | AVX512CD | AVX512VL | AVX512DQ | AVX512BW;
  static constexpr int64_t BMI1 = (1LL << 11);
  static constexpr int64_t BMI2 = (1LL << 12);

  /// Arm features
  static constexpr int64_t ASIMD = (1LL << 32);

  /// Cache enums for L1 (data), L2 and L3
  enum class CacheLevel { L1 = 0, L2, L3, Last = L3 };

  /// CPU vendors
  enum class Vendor { Unknown, Intel, AMD };

  static const CpuInfo* GetInstance();

  /// Returns all the flags for this cpu
  int64_t hardware_flags() const;

  /// Returns the number of cores (including hyper-threaded) on this machine.
  int num_cores() const;

  /// Returns the vendor of the cpu.
  Vendor vendor() const;

  /// Returns the model name of the cpu (e.g. Intel i7-2600)
  const std::string& model_name() const;

  /// Returns the size of the cache in KB at this cache level
  int64_t CacheSize(CacheLevel level) const;

  /// \brief Returns whether or not the given feature is enabled.
  ///
  /// is_supported() is true iff IsDetected() is also true and the feature
  /// wasn't disabled by the user (for example by setting the NEBULA_USER_SIMD_LEVEL
  /// environment variable).
  bool is_supported(int64_t flags) const;

  /// Returns whether or not the given feature is available on the CPU.
  bool IsDetected(int64_t flags) const;

  /// Determine if the CPU meets the minimum CPU requirements and if not, issue an error
  /// and terminate.
  void VerifyCpuRequirements() const;

  /// Toggle a hardware feature on and off.  It is not valid to turn on a feature
  /// that the underlying hardware cannot support. This is useful for testing.
  void EnableFeature(int64_t flag, bool enable);

  bool HasEfficientBmi2() const {
    // BMI2 (pext, pdep) is only efficient on Intel X86 processors.
    return vendor() == Vendor::Intel && is_supported(BMI2);
  }

 private:
  CpuInfo();

  struct Impl;
  std::unique_ptr<Impl> impl_;
};

}  // namespace internal
}  // namespace nebula
